DocumentCode
785905
Title
Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)
Author
Bakir, Muhannad S. ; Reed, Hollie A. ; Thacker, Hiren D. ; Patel, Chirag S. ; Kohl, Paul A. ; Martin, Kevin P. ; Meindl, James D.
Author_Institution
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Volume
50
Issue
10
fYear
2003
Firstpage
2039
Lastpage
2048
Abstract
Sea of Leads (SoL) is an ultrahigh density (>104/cm2) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 × 103/cm2 compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.
Keywords
ULSI; chip scale packaging; fine-pitch technology; indentation; integrated circuit interconnections; microassembling; micromechanical devices; polymer films; GSI; SoL fabrication; electrical performance; embedded air gaps; gigascale integration; in-plane compliance; mechanical performance; mechanically compliant I/O leads; microindentation experiments; packaging; polymer film; sea of leads; ultrahigh density interconnections; wafer-level chip input/output interconnections; wafer-level testing; Air gaps; Costs; Fabrication; Polymer films; Semiconductor device manufacture; Semiconductor device packaging; Semiconductor device testing; Throughput; Wafer scale integration; Wiring;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2003.816528
Filename
1232922
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