A flexible template for H.264/AVC block matching motion estimation architectures

Motion estimation architectures play a fundamental role in nowadays real time video encoding systems. However, in spite of their relevance, the influence of the allocation of the computing resources in terms of the final area, power dissipation and processing speed of such architectures has not been studied in depth in the recent literature. In this sense, a new approach for exploring different allocation alternatives of the computational resources within H.264/AVC block matching motion estimation architectures is presented in this paper. In particular, a novel architectural template is introduced allowing the establishment, in a highly flexible way, of different groups of processing elements (PEs) within one-dimensional motion estimation arrays. The use of this methodology has enabled the evaluation of different design tradeoffs, motivating the introduction of a new architecture composed of four independents groups with four PEs each, able to process CIF@60fps sequences with a reduced equivalent gate count and dynamic power savings.