1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer

Author

Fujisawa, Hiroki ; Nakamura, Masayuki ; Takai, Yasuhiro ; Koshikawa, Yasuji ; Matano, Tatsuya ; Narui, Seiji ; Usuki, Narikazu ; Dono, Chiaki ; Miyatake, Shinichi ; Morino, Makoto ; Arai, Koji ; Kubouchi, Shuichi ; Fujii, Isamu ; Yoko, Hideyuki ; Adachi,

Author_Institution

ELPIDA Memory Inc., Kanagawa, Japan

Volume

40

Issue

4

fYear

2005

fDate

4/1/2005 12:00:00 AM

Firstpage

862

Lastpage

869

Abstract

This paper describes three circuit techniques for a DDR1/DDR2-compatible chip architecture designed for both high-speed and high-density DRAMs: 1) a dual-clock input-latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase one-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 to 2.15 ns; 2) a hybrid multi-oxide output buffer reduces the area penalty of the output buffer caused by compatible chip design from 1.35% to 0.3%; and 3) a quasi-shielded distributed data transfer scheme enables a 2.6-ns reduction in access time to 10.25 ns in both 2-b and 4-b prefetch operations. By using these techniques, we developed a 175.3-mm² 1-Gb SDRAM that operates as an 800-Mb/s/pin DDR2 or 400-Mb/s/pin DDR1.

Keywords

CMOS memory circuits; DRAM chips; flip-flops; high-speed integrated circuits; integrated circuit design; memory architecture; 0.9 ns; 1 Gbit; 1.8 V; 10.25 ns; 2.5 V; 400 Mbit/s; 800 Mbit/s; CMOS integrated circuits; DDR1 compatible chip architecture; DDR2 compatible chip architecture; SDRAM; clock generation; double data rate; dual clock input latch scheme; dual-phase one-shot clock signals; high-density DRAM; high-speed DRAM; hybrid multi-oxide output buffer; latch circuits; prefetch operations; quasishielded distributed data transfer scheme; random input commands; Chip scale packaging; Circuits; Clocks; Latches; Manufacturing; Prefetching; Random access memory; SDRAM; Signal design; Timing; CMOS; Clock; DRAM; SDRAM; clock generation; double data rate (DDR); input latch; output buffer;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.845555

Filename

1424216