• DocumentCode
    786729
  • Title

    Layer assignment for printed circuit boards and integrated circuits

  • Author

    Joy, Donald A. ; Ciesielski, Maciej J.

  • Author_Institution
    Dept. of Comput. & Inf. Sci., Sonoma State Univ., Rohnert Park, CA, USA
  • Volume
    80
  • Issue
    2
  • fYear
    1992
  • fDate
    2/1/1992 12:00:00 AM
  • Firstpage
    311
  • Lastpage
    331
  • Abstract
    The layer assignment problem arises in printed circuit board (PCB) and integrated circuit (IC) design. It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PCBs and ICs. Two types of layer assignment are considered: (1) constrained layer assignment in which routing of interconnections is given and the objective is to assign wires to specific layers, and (2) unconstrained, or topological, layer assignment, in which both the physical routing of interconnections and assignment of the wires to layers is sought. Various objective functions, such as via minimization and minimization of signal delays through interconnect lines are discussed
  • Keywords
    circuit layout; monolithic integrated circuits; network topology; printed circuit design; constrained layer assignment; interconnect wiring; layer assignment problem; network topology; objective functions; printed circuit boards; routing; signal delays; via minimization; Etching; Insulation; Integrated circuit interconnections; Manufacturing; Minimization; Printed circuits; Routing; Very large scale integration; Wires; Wiring;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.123300
  • Filename
    123300