Crosstalk alleviation for dynamic PLAs

The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. However, like all other dynamic circuits, dynamic PLAs have suffered from the crosstalk noise problem. The main reason is that the regularity of the PLA design style causes a product line parallel to the adjacent product lines on the same layer for a long distance so that the crosstalk noise can be significant. Most previous works attempt to prevent the crosstalk noise by adding additional devices or spacing between wires. However, the prevention may degrade performance and increase area/power. In this paper, the authors propose two techniques to alleviate crosstalk noise for dynamic PLAs. The first technique makes use of the fact that depending on the ordering of product lines, some crosstalk does not cause errors in outputs. A proper ordering can greatly reduce the number of product lines affected by crosstalk noise. The authors also observe that the parallel length between two adjacent lines depends on the input and output ordering. For those product lines which can be affected by crosstalk, they attempt to reduce the parallel length by reordering the input and output lines. They have performed experiments on a large set of MCNC benchmark circuits. The results show that after reordering, 86% of product lines become crosstalk immune and need not be considered for crosstalk prevention.