Title :
New hardware-based clock synchronisation for the Byzantine fault
Author :
Yunju Baek ; Heung-Kyu Lee ; Hyunsoo Yoon
Abstract :
A new approach for fault-tolerant clock synchronisation which uses digital clocks instead of the conventional PLLs (phase-locked loops) is presented. In this circuit the delay time of the clock system is much reduced and the exact maximum clock skew is obtained to guarantee the tightness of the synchronisation.
Keywords :
clocks; digital simulation; fault tolerant computing; logic design; synchronisation; Byzantine fault; delay time reduction; digital clocks; fault-tolerant clock synchronisation; hardware-based clock synchronisation; malicious faults; maximum clock skew; purely digital systems; tight synchronisation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19921293
