Damascene W/TiN gate MOSFETs with improved performance for 0.1-μm regime

W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-μm W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, ¹¹⁵In⁺ for NMOS and ¹²¹Sb⁺ for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.