Title :
The Simulation of a new asymmetrical double-gate poly-Si TFT with modified channel conduction mechanism for highly reduced OFF-state leakage current
Author :
Orouji, Ali A. ; Kumar, M. Jagadesh
Author_Institution :
Dept. of Electr. Eng., Semnan Univ., Iran
Abstract :
Poly-Si thin film transistors (TFTs) exhibit large OFF-state reverse leakage currents since their channel conduction is controlled by the gate-induced grain barrier lowering (GIGBL). This also leads to the presence of the pseudosubthreshold region in the transfer characteristic. In this paper, we report a novel poly-Si multiple-gate TFT (MG-TFT), where the front gate consists of three sections with two different materials, in order to reduce the OFF-state leakage current with no significant change in the ON-state current. We demonstrate that the dominant conduction mechanism in the channel can be controlled entirely by the accumulation charge density modulation by the gate (ACMG) instead of the GIGBL, leading to a steep subthreshold slope without any pseudosubthreshold region when compared to an asymmetrical double-gate poly-Si TFT (DG-TFT), resulting in a significantly reduced OFF-state leakage current. Using two-dimensional (2-D) and two-carrier device simulation, we have analyzed the various performance and design considerations of the MG-TFT and explained the reasons for the improved performance of the MG-TFT.
Keywords :
carrier mobility; electrical conductivity; elemental semiconductors; field effect transistors; leakage currents; semiconductor device models; semiconductor device reliability; silicon; thin film transistors; 2D device simulation; Si; accumulation charge density modulation; asymmetrical double-gate thin film transistors; channel conduction mechanism; gate-induced grain barrier lowering; leakage current reduction; multiple-gate thin film transistors; off-state reverse leakage current; two-carrier device simulation; Active matrix liquid crystal displays; Analytical models; Conducting materials; Grain boundaries; Leakage current; MOSFETs; Performance analysis; Semiconductor films; Thin film transistors; Two dimensional displays; Double gate; grain boundary; leakage current; polysilicon; pseudosubthreshold; thin film transistor (TFT); traps; two-dimensional simulation;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2005.860558