A High-Efficiency SOI CMOS Stacked-FET Power Amplifier Using Phase-Based Linearization

A linearization technique based on the phase correction is proposed for a CMOS stacked-FET power amplifier (PA). The linearizer employs a phase injection circuit as a main linearizer. The phase injection circuit presents envelope-reshaped capacitance to the gate of a driver amplifier to correct for phase compression near saturation. It also helps with AM-AM linearization. Hybrid bias circuit consisting of a diode and a resistor is also employed for static adaptive biasing, which allows the PA to meet stringent linearity requirement across the entire power range. Two stacked-FET linear PAs with the proposed linearizers have been designed using a silicon-on-insulator (SOI) CMOS process at 1.88 and 0.9 GHz. The fabricated PAs show adjacent channel leakage ratios (ACLRs) better than -39 dBc with peak power-added efficiencies (PAEs) of 44.3 and 49.2% at 1.88 and 0.9 GHz, respectively, using 3GPP uplink W-CDMA signal.