DocumentCode :
788935
Title :
Dynamic range analysis for the implementation of fast transform
Author :
Wan, Xia ; Wang, Yiliang ; Chen, Wen H.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Volume :
5
Issue :
2
fYear :
1995
fDate :
4/1/1995 12:00:00 AM
Firstpage :
178
Lastpage :
180
Abstract :
An optimal shortest word length implementation of the fast transform based upon mathematical analysis is presented. The flow graph of any fast transform can be expressed as the product of several sparse matrices, where each matrix represents a single pass butterfly operation (i.e., multiplication and accumulation). Each decomposed sparse matrix is analyzed to determine whether a butterfly operation would result in a bit overflow. Additional bits are allocated only to the matrices in which an overflow is likely to occur so that the shortest bit-length implementation is maintained. This methodology is applicable to the shortest bit-length implementation of any fast transform. The application of the proposed method to an existing FDCT algorithm is demonstrated for fixed-point computation
Keywords :
digital arithmetic; discrete cosine transforms; matrix decomposition; minimisation; signal flow graphs; signal processing; sparse matrices; FDCT algorithm; accumulation; bit overflow; decomposed sparse matrix; dynamic range analysis; fast DCT; fast transform; fixed-point computation; flow graph; mathematical analysis; multiplication; optimal shortest word length implementation; shortest bit-length implementation; single pass butterfly operation; sparse matrices; Circuits; Decoding; Discrete cosine transforms; Discrete transforms; Dynamic range; Flow graphs; Matrix decomposition; Signal processing algorithms; Sparse matrices; Very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/76.388068
Filename :
388068
Link To Document :
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