A process integration of high-performance 64-kb MRAM

Author

Kim, Kinam ; Jeong, W.C. ; Koh, K.H. ; Jeong, G.T. ; Park, J.H. ; Lee, S.Y. ; Oh, J.H. ; Song, I.H. ; Jeong, H.S. ; Kinam Kim

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Gyeonggi-Do, South Korea

Volume

39

Issue

5

fYear

2003

Firstpage

2851

Lastpage

2853

Abstract

We have demonstrated fully integrated 64-kb magnetoresistive random access memory (MRAM) using 0.24-μm CMOS technology and discussed some key issues in process integration. Optimal tunneling magnetoresistive (TMR) properties of MRAM bits (37% of TMR ratio and 5-10 kΩ·μm² of RA) were obtained mainly by the control of bottom electrode roughness, and electrical shorting was avoided by some commercialized wet solutions. In viewpoint of process integration, excellent TMR properties of magnetic tunnel junction (MTJ) fresh films and prevention of their degradation in post patterning process are two crucial factors, and especially, electrical shorting requires some careful control.

Keywords

CMOS integrated circuits; giant magnetoresistance; magnetic storage; magnetoresistive devices; random-access storage; 0.24 micron; 0.24-μm CMOS technology; 64 kbit; bottom electrode roughness; commercialized wet solutions; electrical shorting; high-performance 64-kb MRAM; magnetoresistive random access memory; post patterning process; process integration; tunneling magnetoresistive properties; CMOS process; CMOS technology; Commercialization; Electrodes; Magnetic films; Magnetic properties; Magnetic tunneling; Optimal control; Random access memory; Tunneling magnetoresistance;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/TMAG.2003.816243

Filename

1233237