Noise margin and leakage in ultra-low leakage SRAM cell design

Author

Hook, Terence B. ; Breitwisch, Matt ; Brown, Jeff ; Cottrell, P. ; Hoyniak, Dennis ; Lam, Chung ; Mann, Randy

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

Volume

49

Issue

8

fYear

2002

fDate

8/1/2002 12:00:00 AM

Firstpage

1499

Lastpage

1501

Abstract

Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon.

Keywords

CMOS memory circuits; SRAM chips; fluctuations; integrated circuit noise; leakage currents; low-power electronics; stability; CMOS memory ICs; SRAM cell design; beta ratio; chip performance; random dopant fluctuations; stability; static noise margin; static random-access memories; threshold uncertainty; threshold voltage; ultra-low leakage SRAM cell; ultra-low power cell; CMOS memory circuits; Fluctuations; Gate leakage; Power supplies; Random access memory; Read-write memory; Stability; Temperature; Threshold voltage; Uncertainty;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2002.801433

Filename

1019942