Fast timing recovery for linearly and nonlinearly modulated systems

Digital phase lock loops (PLLs) are often used in timing acquisition systems. It is known that some non-data-aided timing error detectors occasionally cause hangup problems in digital PLLs. In this paper, we introduce a novel two step antihangup timing recovery scheme. Through intensive simulations, we show that this enhanced scheme greatly reduces the probability of hangup, and speeds up the timing recovery process for both linearly and nonlinearly modulated systems.