DocumentCode :
789832
Title :
Optimisation of Reed-Muller PLA implementations
Author :
Wang, L. ; Almaini, A.E.A.
Author_Institution :
Altera Eur. Technol. Centre, High Wycombe, UK
Volume :
149
Issue :
2
fYear :
2002
fDate :
4/1/2002 12:00:00 AM
Firstpage :
119
Lastpage :
128
Abstract :
Decomposition techniques are utilised for mixed polarity Reed-Muller minimisation, which lead to Reed-Muller programmable logic array implementations for Boolean functions. The proposed algorithm produces a simplified mixed polarity Reed-Muller format from the conventional sum-of-products input based on a top-down strategy. The output format belongs to the most general class of AND/XOR forms, namely exclusive-OR sum-of-products. This method is further generalised to very large multiple output Boolean functions. The developed decomposition method is implemented in the C language and tested with MCNC and IWLS´93 benchmarks. Experimental results show that the decomposition method can produce much better results than Espresso for many test cases. This efficient method offers compact Reed-Muller programmable logic array implementations with the added advantage of easy testability, in contrast to the conventional programmable logic array realisations
Keywords :
Boolean functions; Reed-Muller codes; binary decision diagrams; circuit complexity; minimisation of switching nets; programmable logic arrays; AND/XOR forms; Boolean functions; Reed-Muller programmable logic array; benchmarks; binary decision diagram; decomposition techniques; exclusive-OR sum-of-products; functional verification; implementation optimisation; majority m-cube; mixed polarity Reed-Muller minimisation; prime implicants; simplified mixed polarity format; testability; top-down approach; very large multiple output functions;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:20020354
Filename :
1020018
Link To Document :
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