A noise optimization technique for integrated low-noise amplifiers

Author

Goo, Jung-Suk ; Ahn, Hee-Tae ; Ladwig, Donald J. ; Yu, Zhiping ; Lee, Thomas H. ; Dutton, Robert W.

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

Volume

37

Issue

8

fYear

2002

fDate

8/1/2002 12:00:00 AM

Firstpage

994

Lastpage

1002

Abstract

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF_min by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 μm CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; circuit optimisation; integrated circuit noise; 0.24 micron; 0.9 dB; 2.0 V; 7.5 mW; 800 MHz; CMOS technology; RF circuit design; four-noise parameters; integrated low-noise amplifier; minimum noise figure; noise optimization; source degeneration inductance; source impedance; third-order input intercept point; two-port noise theory; CMOS technology; Design optimization; Geometry; Impedance; Inductance; Low-noise amplifiers; Noise figure; Noise measurement; Power amplifiers; Power supplies;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.800956

Filename

1020238