A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

Author

Kan, Toby K K ; Leung, Gerry C T ; Luong, Howard C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

37

Issue

8

fYear

2002

fDate

8/1/2002 12:00:00 AM

Firstpage

1012

Lastpage

1020

Abstract

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 μm digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000×1000 μm² and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 μs and the total power consumption is 95 mW.

Keywords

CMOS analogue integrated circuits; circuit tuning; frequency synthesizers; integrated circuit noise; phase noise; voltage-controlled oscillators; 0.5 micron; 1.8 GHz; 1.8492 to 1.8698 GHz; 128 mus; 2 V; 356 to 931 MHz; 95 mW; fully-integrated CMOS dual-loop frequency synthesizer; phase noise; power consumption; ring-type VCO; settling time; tuning range; wireless communication; Area measurement; CMOS process; Communication standards; Frequency synthesizers; Noise measurement; Phase noise; Tuning; Voltage; Voltage-controlled oscillators; Wireless communication;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.800977

Filename

1020240