A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis

Author

Perrott, Michael H. ; Trott, Mitchell D. ; Sodini, Charles G.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

Volume

37

Issue

8

fYear

2002

fDate

8/1/2002 12:00:00 AM

Firstpage

1028

Lastpage

1038

Abstract

A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of Σ-Δ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom Σ-Δ synthesizer implemented in a 0.6 μm CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.

Keywords

CMOS analogue integrated circuits; frequency synthesizers; integrated circuit modelling; integrated circuit noise; phase locked loops; phase noise; sigma-delta modulation; Σ-Δ fractional-N frequency synthesizer; 0.6 micron; 25 kHz to 10 MHz; CMOS process; divide value; dynamic model; phase noise; phase-locked loop; CMOS process; Circuit noise; Frequency synthesizers; Laboratories; Legged locomotion; Noise measurement; Performance analysis; Phase locked loops; Phase noise; Semiconductor device modeling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.800925

Filename

1020242