Title :
A direct digital period synthesis circuit
Author :
Calbaza, Dorin Emil ; Savaria, Yvon
Author_Institution :
Gennum Corp., Burlington, Ont., Canada
fDate :
8/1/2002 12:00:00 AM
Abstract :
This paper presents a direct digital period synthesis (DDPS) circuit, which combines the DDS´ ability to control the frequency, with the speed and accuracy of a delay-locked-loop-based frequency multiplier. The resulting DDPS circuit can synthesize clocks with accurately controlled periods. It can do clean and accurate transitions from a first target period to a second target period, both periods having precisely specified durations. A prototype integrated circuit reported in this paper, implemented in 0.25 μm CMOS technology, synthesizes clocks with frequencies up to 500 MHz and peak-to-peak jitter measured at 208 ps.
Keywords :
CMOS digital integrated circuits; clocks; direct digital synthesis; timing jitter; 0.25 micron; 500 MHz; CMOS integrated circuit; clock synthesis; delay-locked-loop; direct digital period synthesis circuit; frequency control; frequency multiplier; jitter; CMOS integrated circuits; CMOS technology; Circuit synthesis; Clocks; Delay; Frequency synthesizers; Integrated circuit synthesis; Integrated circuit technology; Jitter; Prototypes;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.800923
