Title :
A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection
Author :
GUO, Chunbing ; Lo, Chi-Wa ; Choi, Yu-Wing ; Hsu, Issac ; Kan, Toby ; Leung, David ; Chan, Alan ; Luong, Howard C.
Author_Institution :
Dept. of Electron. & Electr. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
fDate :
8/1/2002 12:00:00 AM
Abstract :
A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-μm CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm2. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 μs.
Keywords :
CMOS analogue integrated circuits; UHF filters; UHF mixers; cellular radio; phase locked loops; radio receivers; sigma-delta modulation; 227 mW; 900 MHz; ADC; automatic gain control; fractional-N synthesizer; fully integrated receiver; high-Q channel-selection filter; image rejection; lossy on-chip inductors; low settling time; low-noise amplifier; mixers; monolithic CMOS wireless receiver; on-chip RF filters; on-chip filters; phase noise; phase-locked loop synthesizer; short-distance wireless communication; sigma-delta modulator; single chip; variable gain amplifier; Area measurement; CMOS image sensors; CMOS process; Filters; Measurement standards; Noise measurement; Power measurement; Radio frequency; Synthesizers; Wireless sensor networks;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.800981
