DocumentCode :
790464
Title :
Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary
Author :
Nunez-Yanez, J.L. ; Chouliaras, V.A.
Author_Institution :
Dept. of Electron. Eng., Univ. of Bristol, UK
Volume :
153
Issue :
1
fYear :
2006
Firstpage :
47
Lastpage :
58
Abstract :
A high-throughput lossless data compression IP core built around a CAM-based dictionary whose number of available entries and data word width adjust to the characteristics of the incoming data stream is presented. These two features enhance model adaptation to the input data, improving compression efficiency, and enable greater throughputs as a multiplicity of bytes can be processed per cycle. A parsing mechanism adjusts the width of dictionary words to natural words while the length of the dictionary grows from an initial empty state to a maximum value defined as a run-time configuration parameter. The compressor/decompressor architecture was prototyped on an FPGA-based PCI board. An ASIC hard-macro was subsequently implemented and achieved a throughput of more than 1 gigabyte per second when clocking at 277 MHz on a high-performance, 0.13 μm, eight-layer copper CMOS process.
Keywords :
CMOS logic circuits; application specific integrated circuits; data compression; dictionaries; field programmable gate arrays; ASIC; FPGA-based PCI board; IP core; compressor/decompressor architecture; configurable variable-geometry CAM dictionary; data stream; lossless data compression hardware; parsing mechanism;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:20045130
Filename :
1576341
Link To Document :
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