DocumentCode :
790518
Title :
Design space exploration of a software speculative parallelization scheme
Author :
Cintra, Marcelo ; Llanos, Diego R.
Author_Institution :
Sch. of Informatics, Edinburgh Univ., UK
Volume :
16
Issue :
6
fYear :
2005
fDate :
6/1/2005 12:00:00 AM
Firstpage :
562
Lastpage :
576
Abstract :
With speculative parallelization, code sections that cannot be fully analyzed by the compiler are optimistically executed in parallel. Hardware schemes are fast but expensive and require modifications to the processors and/or memory system. Software schemes require no changes to the hardware of existing shared-memory systems, but can suffer from significant overheads involved with the speculative execution. In fact, the performance of software schemes is highly dependent on application characteristics, the design and implementation of the scheme, and the system configuration and size. This paper explores the design space of a recently proposed software speculative parallelization scheme. In the process, we gain insight into the most beneficial features of software schemes for speculative parallelization, as well as the most influential application characteristics. For instance, experimental results show that, contrary to intuition, checking for data dependence violations on every speculative store, as opposed to at commit time, leads to little performance degradation in the worst case and to significantly better performance with large configurations. Also, scheduling policies based on windows can perform very close to fully dynamic policies with a fraction of the memory overhead. Finally, experimental results show consistent speedups in the execution of loops that cannot be parallelized at compile time, both with and without RAW data dependences, for 4 to 32 processors.
Keywords :
parallel architectures; parallel programming; parallelising compilers; program control structures; program diagnostics; shared memory systems; compiler code analysis; data dependence violation checking; design space exploration; loop execution; parallel architecture; scheduling policy; software speculative parallelization scheme; thread-level speculation; Application software; Degradation; Dynamic scheduling; Hardware; Optimizing compilers; Parallel architectures; Processor scheduling; Software performance; Software systems; Space exploration; Speculative parallelization; parallel architectures.; thread-level speculation;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/TPDS.2005.69
Filename :
1425444
Link To Document :
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