DocumentCode :
790659
Title :
Finite buffer realization of input-output discrete-event systems
Author :
Kumar, Ratnesh ; Garg, Vijay K. ; Marcus, Steven I.
Author_Institution :
Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Volume :
40
Issue :
6
fYear :
1995
fDate :
6/1/1995 12:00:00 AM
Firstpage :
1042
Lastpage :
1053
Abstract :
Many discrete-event systems (DES´s), such as manufacturing systems, database management systems, communication networks, traffic systems, etc., can be modeled as input-output discrete-event systems (I/O DES´s). In this paper we formulate and study the problem of stable realization of such systems in the logical setting. Given an input and an output language describing the sequences of events that occur at the input and output, respectively, of an I/O DES, we study whether it is possible to realize the system as a unit consisting of a given set of buffers of finite capacity, called a dispatching unit. The notions of stable, conditionally stable, dispatchable and conditionally dispatchable units are introduced as existence of stable (or input-output bounded), and causal (or prefix preserving) input-output maps, and effectively computable necessary and sufficient conditions for testing them are obtained
Keywords :
discrete event systems; formal languages; input-output stability; production control; causal input-output maps; dispatching unit; finite buffer realization; input language; input-output discrete-event systems; manufacturing systems; necessary condition; output language; prefix preserving maps; sufficient conditions; Automata; Communication networks; Database systems; Discrete event systems; Dispatching; Interleaved codes; Manufacturing systems; Sufficient conditions; Telecommunication traffic; Traffic control;
fLanguage :
English
Journal_Title :
Automatic Control, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9286
Type :
jour
DOI :
10.1109/9.388681
Filename :
388681
Link To Document :
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