Title :
500 V, N-Channel atomic lattice layout (ALL) IGBT´s with superior latching immunity
Author :
Parthasarathy, Vijay ; So, K.C. ; Shen, Z. ; Chow, T. Paul
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
fDate :
7/1/1995 12:00:00 AM
Abstract :
Experimental and simulation results for the impact of Atomic Lattice Layout (ALL) geometry on the latchup performance of 500 V n-channel IGBT´s is reported here for the first time and is compared to the conventional square, hexagonal and stripe geometries. It is shown that the ALL cell IGBT´s provide a superior trade-off between optimization of forward drop and latching current with a small penalty in the forward drop.<>
Keywords :
insulated gate bipolar transistors; power bipolar transistors; semiconductor device reliability; 500 V; atomic lattice layout; forward drop; latching current; latching immunity; latchup performance; n-channel IGBT; n-channel transistors; power transistors; Avalanche breakdown; Breakdown voltage; Geometry; Insulated gate bipolar transistors; Ionization; Lattices; Semiconductor optical amplifiers; Senior members; Solid modeling; Turning;
Journal_Title :
Electron Device Letters, IEEE
