DocumentCode :
791463
Title :
Evaluation of the parallelization potential for efficient multimedia implementations: dynamic evaluation of algorithm critical path
Author :
Prihozhy, Anatoly ; Mattavelli, Marco ; Mlynek, Daniel
Author_Institution :
Signal Process. Lab. of the Fed. Inst. of Technol. of Lausanne, Switzerland
Volume :
15
Issue :
5
fYear :
2005
fDate :
5/1/2005 12:00:00 AM
Firstpage :
593
Lastpage :
608
Abstract :
This paper presents a model metrics and a methodology for evaluating the critical path on the data flow execution graph (DFEG) of multimedia algorithms specified as C programs. The paper describes an efficient dynamic critical path evaluation approach that generates no explicit execution graph. Such approach includes two key stages: 1) the instrumentation of the C code and the mapping into a C++ code version and 2) the execution of the C++ code under real input data and finally the actual dynamic evaluation of the critical path. The model metrics and the software analysis methodologies aim at the estimation and at the increase of the upper bound of execution speed and parallelization potential. Both metrics and methodology are particularly tailored for application with complex multimedia algorithms. Critical path analysis and the subsequent algorithmic development stage is a fundamental methodological preliminary step for the efficient definition of architectures when the objective is the implementation of the multimedia algorithm on systems-on-chips or heterogeneous platforms.
Keywords :
digital signal processing chips; multimedia communication; software tools; system-on-chip; algorithm critical path; data flow execution graph; digital signal processor; dynamic critical path evaluation approach; multimedia algorithm; parallelization potential; software analysis methodology; systems-on-chip; Acceleration; Algorithm design and analysis; Flow graphs; Heuristic algorithms; Instruments; Laboratories; Multimedia systems; Partitioning algorithms; Signal processing; Signal processing algorithms; Algorithm transformation; architecture design; critical path; data flow execution graph (DFEG); digital signal processor (DSP) acceleration; multimedia algorithms; parallelization potential;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/TCSVT.2005.846427
Filename :
1425525
Link To Document :
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