Title :
Bridging fault modeling and simulation for deep submicron CMOS ICs
Author :
Favalli, Michele ; Dalpasso, Marcello
Author_Institution :
Dept. of Eng., Ferrara Univ., Italy
fDate :
8/1/2002 12:00:00 AM
Abstract :
Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage metric. Conditions are defined to ensure that (under steady-state conditions) either a fault is detected by a test sequence or it will not give rise to errors for any other input, independently of the actual values of IC parameters. Such a fault model has been implemented in a simulator and validated over combinational benchmarks.
Keywords :
CMOS logic circuits; VLSI; combinational circuits; fault simulation; integrated circuit testing; logic testing; network parameters; symbol manipulation; IC parameters; bridging fault modeling; bridging fault simulation; combinational benchmarks; coverage metric; deep submicron CMOS ICs; high-quality testing; process parameters; steady-state conditions; symbolic simulation; test sequence; CMOS logic circuits; CMOS technology; Circuit faults; Electrical fault detection; Fault detection; Integrated circuit testing; Logic devices; Logic testing; Performance evaluation; Semiconductor device modeling;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2002.800457
