DocumentCode :
792587
Title :
Germanium MOS capacitors incorporating ultrathin high-/spl kappa/ gate dielectric
Author :
On Chui, Chi ; Ramanathan, Shriram ; Triplett, Baylor B. ; McIntyre, Paul C. ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Volume :
23
Issue :
8
fYear :
2002
Firstpage :
473
Lastpage :
475
Abstract :
For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.
Keywords :
MOS capacitors; annealing; dielectric thin films; germanium; passivation; sputter deposition; 410 C; 5 to 8 angstrom; Ge; MOS capacitors; ZrO/sub 2/; capacitance-based equivalent oxide thickness; capacitance-voltage characteristics; device uniformity; device yield; forming gas anneal; low thermal budget process; native oxide interlayer removal; relative thermodynamic instability; sputtering; surface passivation; ultrathin high-permittivity gate dielectric; zirconia gate dielectric; Annealing; Capacitance; Capacitance-voltage characteristics; Dielectric materials; Dielectric substrates; Fabrication; Germanium; MOS capacitors; Temperature; Zirconium;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2002.801319
Filename :
1021097
Link To Document :
بازگشت