Title :
N-channel 3C-SiC MOSFETs on silicon substrate
Author :
Wan, Jianwei ; Capano, M.A. ; Melloch, Michael R. ; Cooper, James A., Jr.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Inversion-mode, n-channel 3C-SiC MOSFETs have been fabricated in a 3C-SiC epilayer grown on a 2°-off-axis Si(001) substrate with optimized SiC processing techniques. Phosphorus implantations are employed for source/drain formation and a sheet resistance of 70 Ω per square is obtained after annealing at 1250°C for 30 min in argon. Both drain characteristics and subthreshold characteristics show typical transistor behavior with an effective channel mobility of 165 cm2/Vs. The breakdown field of the gate oxide is about 3.5 MV/cm.
Keywords :
MOSFET; annealing; carrier mobility; chemical vapour deposition; etching; inversion layers; ion implantation; leakage currents; oxidation; semiconductor device breakdown; silicon compounds; wide band gap semiconductors; 1250 C; 30 min; 3C-SiC epilayer; CVD; Si; SiC; annealing; contact resistance; effective channel mobility; gate oxide breakdown field; inversion-mode; leakage current; n-channel MOSFET; ohmic characteristic; optimized processing techniques; phosphorus implantations; planar structures; polysilicon gate; sheet resistance; source/drain formation; spin-on phosphorus; subthreshold characteristics; transmission line method test structures; wet etching; wet oxidation; wide band gap; Annealing; Argon; Electric breakdown; MOSFETs; Oxidation; Silicon carbide; Silicon compounds; Substrates; Thermal conductivity; Wet etching;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2002.801259
