• DocumentCode
    792684
  • Title

    Impacts of gate structure on dynamic threshold SOI nMOSFETs

  • Author

    Lo, Wen-Cheng ; Chang, Sun-Jay ; Chang, Chun-Yen ; Tien-Sheng Cao

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    23
  • Issue
    8
  • fYear
    2002
  • Firstpage
    497
  • Lastpage
    499
  • Abstract
    The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.
  • Keywords
    MOSFET; buried layers; silicon-on-insulator; DTMOS-mode operation; H-gate; LPCVD; SOI nMOSFET; Si-SiO/sub 2/; T-gate; body effect factor; drain-induced-barrier-lowering; driving current; dynamic threshold voltage; gate structure; next generation ULSI; passivation oxide; rapid thermal annealing; substrate-contact structures effect; Chaos; Circuits; Implants; Insulation; Isolation technology; MOSFETs; Senior members; Silicon on insulator technology; Threshold voltage; Ultra large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2002.801334
  • Filename
    1021105