A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

Author

Leung, Ka Nang ; Mok, Philip K T

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

Volume

38

Issue

10

fYear

2003

Firstpage

1691

Lastpage

1702

Abstract

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-μm CMOS technology, and the active chip area is 568 μm×541 μm. The total error of the output voltage due to line and load variations is less than ±0.25%, and the temperature coefficient is 38 ppm/°C. Moreover, the output voltage can recover within 2 μs for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 μV/√Hz, respectively.

Keywords

CMOS integrated circuits; circuit stability; compensation; damping; reference circuits; system-on-chip; transient response; voltage regulators; 0.6 micron; 1.5 V; 100 mA; CMOS low-dropout regulator; capacitor-free operation; damping-factor-control frequency compensation; loop-gain stability; output noise spectral density; power supply rejection ratio; system-on-chip; temperature coefficient; transient response; voltage reference circuit; CMOS technology; Frequency; Load management; Pins; Regulators; Space technology; Stability; System-on-a-chip; Temperature; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.817256

Filename

1233757