Title :
Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si
Author :
Nayfeh, Ammar ; Chui, Chi On ; Yonehara, Takao ; Saraswat, Krishna C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
fDate :
5/1/2005 12:00:00 AM
Abstract :
We have successfully demonstrated high-performance p-MOSFETs in germanium grown directly on Si using a novel heteroepitaxial growth technique, which uses multisteps of hydrogen annealing and growth to confine misfit dislocations near the Ge-Si interface, thus not threading to the surface as expected in this 4.2% lattice-mismatched system. We used a low thermal budget process with silicon dioxide on germanium oxynitride (GeOxNy) gate dielectric and Si0.75Ge0.25 gate electrode. Characterization of the device using cross-sectional transmission electron microscopy and atomic force microscopy at different stages of the fabrication illustrates device-quality interfaces that yielded hole effective mobility as high as 250 cm2/Vs.
Keywords :
Ge-Si alloys; MOSFET; atomic force microscopy; chemical vapour deposition; epitaxial growth; germanium compounds; rapid thermal annealing; transmission electron microscopy; Ge-Si interface; GeON; MOS devices; Si0.75Ge0.25; atomic force microscopy; device-quality interfaces; effective mobility; gate dielectric; gate electrode; germanium oxynitride; heteroepitaxial growth technique; hydrogen annealing; misfit dislocations; p-MOSFET; silicon dioxide; thermal budget process; transmission electron microscopy; Annealing; Atomic force microscopy; Dielectrics; Electrodes; Fabrication; Germanium; Hydrogen; MOSFET circuits; Silicon compounds; Transmission electron microscopy; Anneal; MOS devices; dislocations; effective field; effective mobility; germanium; germanium oxynitride (GOI); heteroepitaxy; hydrogen; mobility;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2005.846578