Title :
A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation
Author :
Lee, Hoi ; Leung, Ka Nang ; Mok, Philip K T
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-μm CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V/μs average slew rate while only dissipating 330 μW at 1.5 V, when driving a 25-kΩ//120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.
Keywords :
CMOS analogue integrated circuits; amplifiers; compensation; frequency response; integrated circuit design; low-power electronics; network topology; transient response; 0.6 micron; 100 dB; CMOS process; average slew rate; bandwidth improvement; bandwidth-to-power efficiency; dual-loop parallel compensation; dual-path bandwidth extension amplifier topology; frequency compensation; gain-bandwidth product; high-frequency signal propagation; large-signal transient response; low-power three-stage amplifiers; parallel high-speed paths; power dissipation; slew rate improvement; slew-rate-to-power efficiency; small-signal frequency response; Bandwidth; CMOS process; Capacitors; Circuit topology; Frequency locked loops; Gain; Network topology; Output feedback; Stability; Transconductance;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.817597
