An 8-bit 100-MHz CMOS linear interpolation DAC

Author

Zhou, Yijun ; Yuan, Jiren

Author_Institution

Inst. for Infocomm Res. (I2R), Singapore, Singapore

Volume

38

Issue

10

fYear

2003

Firstpage

1758

Lastpage

1761

Abstract

An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC´s image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-μm double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm × 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.

Keywords

CMOS integrated circuits; delay lines; digital-analogue conversion; frequency response; interpolation; mixed analogue-digital integrated circuits; 0.35 micron; 0.67 mm; 100 MHz; 3.3 V; 54.5 mW; 8 bit; 8-bit 100-MHz CMOS linear interpolation DAC; 8-bit binary-weighted DAC; DAC image component attenuation; analog reconstruction filter; chip core size; digital-to-analog converter; double-poly triple-metal CMOS process; evenly skewed clocks; linear interpolation function; single-chip integration; time-interleaved structure; total power consumption; voltage-controlled delay line; wireless transmitter; Attenuation; CMOS process; Clocks; Delay lines; Digital-analog conversion; Filters; Image reconstruction; Interpolation; Transmitters; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.817593

Filename

1233797