A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS

Author

Moon, Yongsam ; Lee, Sang-Hyun ; Shim, Daeyun

Author_Institution

Silicon Image Inc., Sunnyvale, CA, USA

Volume

40

Issue

5

fYear

2005

fDate

5/1/2005 12:00:00 AM

Firstpage

1175

Lastpage

1179

Abstract

A divide-by-16.5 frequency divider, providing read- and write-clocks for an elastic buffer or a gearbox between 10.3125-Gb/s and quad 3.125-Gb/s transceivers in 10-G Ethernet application, is presented. The high-speed and noninteger division is designed by cascading high-speed divide-by-3 followed by divide-by-5.5 which uses double-edge-triggered flip-flops. The divide-by-3 circuit receives and generates 5.15625-GHz and 1.71875-GHz differential clocks with a 50% duty cycle, respectively. Based on current-mode logics (CMLs), the proposed divide-by-16.5 scheme is implemented in a 0.13-μm CMOS technology to achieve over 5-GHz operation while consuming 18 mW from a 1.2-V supply.

Keywords

CMOS integrated circuits; clocks; current-mode logic; flip-flops; frequency dividers; integrated circuit design; local area networks; transceivers; 0.13 micron; 1.2 V; 1.71875 GHz; 18 mW; 5 GHz; 5.15625 GHz; CMOS technology; Ethernet transceiver; circuit receives; current-mode logics; divide-by-16.5 circuit; double edge triggered flip-flop; elastic buffer; frequency divider; gearbox; noninteger division; read-and write-clocks; CMOS logic circuits; CMOS technology; Circuit synthesis; Circuit testing; Clocks; Ethernet networks; Flip-flops; Frequency conversion; Timing; Transceivers; 10-Gb Ethernet; Current-mode logic (CML); divide-by-16.5; double-edge-triggered flip-flop (DTFF); frequency divider;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.845994

Filename

1425725