DocumentCode
793803
Title
A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process
Author
Shirahama, Masanori ; Agata, Yasuhiro ; Kawasaki, Toshiaki ; Nishihara, Ryuji ; Abe, Wataru ; Kuroda, Naoki ; Sadakata, Hiroyuki ; Uchikoba, Toshitaka ; Takahashi, Kazunari ; Egashira, Kyoko ; Honda, Shinji ; Miura, Miho ; Hashimoto, Shin ; Kikukawa, Hiro
Author_Institution
Syst. LSI Technol. Dev. Center, Corp. Syst. LSI Dev. Div., Kyoto, Japan
Volume
40
Issue
5
fYear
2005
fDate
5/1/2005 12:00:00 AM
Firstpage
1200
Lastpage
1207
Abstract
This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D2RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D2RAM fabricated by a 0.15-μm standard CMOS process.
Keywords
CMOS memory circuits; DRAM chips; large scale integration; 0.15 micron; 400 MHz; CMOS process; LSI; dual-port interleaved DRAM; embedded DRAM; large-scale memories; noise element breakdowns; random cycle access; signal-loss compensating technology; striped trench capacitor; write-before-sensing circuit; write-bus; CMOS process; CMOS technology; Capacitance; Costs; Decoding; Large scale integration; Random access memory; Read-write memory; Semiconductor device noise; Standards development; CMOS-compatible; embedded DRAM; random cycle; trench;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2005.845995
Filename
1425728
Link To Document