Title :
Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate
Author :
Dong-Il Moon ; Sung-Jin Choi ; Duarte, Juan Pablo ; Yang-Kyu Choi
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.
Keywords :
elemental semiconductors; field effect transistors; flash memories; iterative methods; nanowires; silicon; sputter etching; 3D stacked flash memory; GAA structure; JL FET; Si; bulk substrate; bulk wafer; channel dimensions; deep RIE process; deep reactive ion etching process; gate-all-around structure; iterations; junction-free structure; junctionless field-effect transistor; on-state current; silicon nanowire gate-all-around junctionless transistors; Doping; Etching; Field effect transistors; Logic gates; Silicon; Substrates; Bosch process; bulk MOSFET; corner effect; deep reactive ion etching (RIE); extension doping; gate-all-around (GAA); junctionless (JL) transistor; short-channel effects (SCEs); vertically stacked silicon nanowire (Si-NW);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2013.2247763
