• DocumentCode
    793996
  • Title

    Synthesis of SPP three-level logic networks using affine spaces

  • Author

    Ciriani, Valentina

  • Author_Institution
    Dept. of Informatics, Univ. of Pisa, Italy
  • Volume
    22
  • Issue
    10
  • fYear
    2003
  • Firstpage
    1310
  • Lastpage
    1323
  • Abstract
    Recently defined, three-level logic sum of pseudo-products (SPP) forms are EXOR-AND-OR networks representing Boolean functions, and are much shorter than standard two-level sum of products (SOP) expressions (Luccio and Pagli, 1999). The main disadvantages of SPP networks are their cumbersome theory in the original formulation and their high minimization time. In addition, the current technology cannot efficiently implement the unbounded fanin EXOR gates of SPP expressions. In this paper, we rephrase SPP theory in an algebraic context to obtain an easier description of the networks. We define a new model of SPP networks (k-SPP) with bounded fanin EXOR gates, whose minimization time is strongly reduced and whose minimal forms are still very compact. In the Boolean space {0,1}n, a k-SPP form contains EXOR gates with at most k literals, where 1 ≤ k ≤ n. The limit case k = n corresponds to SPP networks and k = 1 to SOPs. Finally, we perform an extensive set of experiments on classical benchmarks. In order to validate our approach, the results are compared with those obtained for the major two- and three-level forms using standard metrics.
  • Keywords
    Boolean functions; logic CAD; logic gates; minimisation of switching nets; multivalued logic circuits; Boolean functions; Boolean space; EXOR-AND-OR networks; SPP three-level logic networks; affine spaces; minimal forms; minimization time; three-level forms; three-level logic sum of pseudo-products; unbounded fanin EXOR gates; Arithmetic; Boolean functions; Circuit synthesis; Design optimization; Informatics; Logic circuits; Logic design; Minimization methods; Network synthesis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2003.818121
  • Filename
    1233818