DocumentCode
794031
Title
Effective free space management for cut-based placement via analytical constraint generation
Author
Alpert, Charles J. ; Nam, Gi-Joon ; Villarrubia, Paul G.
Author_Institution
IBM Corp., Austin, TX, USA
Volume
22
Issue
10
fYear
2003
Firstpage
1343
Lastpage
1353
Abstract
IP blocks and large macro cells are becoming more prevalent in the physical layout of a design, actually causing an increase in the available free space. We observe that top-down placement based on recursive bisection with multilevel partitioning performs poorly on these porous designs since it lacks a global view of the ideal placement. However, the strength of analytic placement methods lies in their ability to ascertain this global view. Consequently, we propose an enhancement to cut-based placement called analytic constraint generation (ACG). ACG utilizes an analytic engine to distribute available free space appropriately by determining balance constraints for each partitioning step. For one-dimensional placements, our experiments illustrate the large gap between analytic engines, traditional cut-based placement, and ACG as a design becomes increasingly sparse. We also show that for real industry designs, ACG significantly improves the performance of cut-based placement, particularly timing perspective, as implemented within a state-of-the-art industrial placer.
Keywords
cellular arrays; circuit layout CAD; integrated circuit layout; logic CAD; logic partitioning; timing; analytic constraint generation; analytic engines; analytical constraint generation; available free space; balance constraints; cut-based placement; free space management; industrial placer; multilevel partitioning; one-dimensional placements; physical layout; porous designs; recursive bisection; timing perspective; top-down placement; Algorithm design and analysis; Analytical models; Constraint optimization; Design automation; Engines; Integrated circuit layout; Logic; Partitioning algorithms; Simulated annealing; Timing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2003.818126
Filename
1233820
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