DocumentCode :
794113
Title :
Wordlength optimization for linear digital signal processing
Author :
Constantinides, George A. ; Cheung, Peter Y K ; Luk, Wayne
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll., London, UK
Volume :
22
Issue :
10
fYear :
2003
Firstpage :
1432
Lastpage :
1442
Abstract :
This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are proposed, one which guarantees an optimum set of wordlengths for each internal variable, and one which is a heuristic approach. Both techniques allow the user to tradeoff implementation area for arithmetic error at system outputs. Optimality (with respect to the area and error estimates) is guaranteed through modeling as a mixed integer linear program. It is demonstrated that the proposed heuristic leads to area improvements of 6% to 45% combined with speed increases compared to the optimum uniform wordlength design. In addition, the heuristic reaches within 0.7% of the optimum multiple wordlength area over a range of benchmark problems.
Keywords :
circuit layout CAD; circuit optimisation; digital signal processing chips; directed graphs; integer programming; integrated circuit layout; linear programming; parallel architectures; area improvements; arithmetic error; benchmark problems; custom parallel processing units; design automation; directed graph; heuristic approach; implementation area; linear digital signal processing; linear time-invariant applications; mixed integer linear program; optimality guarantee; optimum multiple wordlength area; optimum set of wordlengths; wordlength allocation problem; wordlength optimization; Arithmetic; Control system synthesis; Design automation; Digital signal processing; Digital signal processors; Field programmable gate arrays; Parallel processing; Quantization; Signal processing; Signal synthesis;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.818119
Filename :
1233828
Link To Document :
بازگشت