Title :
The architecture of a high performance mass store with GMR memory cells
Author :
Pohm, A.V. ; Daughton, J.M. ; Brown, J. ; Beech, R.
Author_Institution :
Nonvolatile Electron., Eden Prairie, MN, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
A high output, GMR, sub-micron memory cell has been designed for a 16 Megabit die with an area of 0.9 square cm. Using die parameters, a study was made of a wafer scale, high performance memory system with on board cache units. The study shows that gigabyte per second throughputs can be achieved while using modest power
Keywords :
cache storage; giant magnetoresistance; integrated memory circuits; magnetic film stores; magnetoresistive devices; memory architecture; 10 W; 16 Mbit; GMR memory cells; die parameters; gigabyte per second throughput; high output GMR submicron memory cell; high performance mass store; on board cache units; peak power; wafer memory organization; wafer scale high performance memory system; Anisotropic magnetoresistance; Bandwidth; Contact resistance; Energy consumption; Giant magnetoresistance; Large-scale systems; Lithography; Manufacturing; Nonvolatile memory; Throughput;
Journal_Title :
Magnetics, IEEE Transactions on
