DocumentCode
794398
Title
Four state asynchronous architectures
Author
McAuley, Anthony J.
Author_Institution
Bellcore, Morristown, NJ, USA
Volume
41
Issue
2
fYear
1992
fDate
2/1/1992 12:00:00 AM
Firstpage
129
Lastpage
142
Abstract
An approach is presented to high-performance asynchronous architectures offering significant advantages over conventional clocked systems, without some of the drawbacks normally associated with asynchronous techniques. As the level of integration increases, an asynchronous wavefront array designed using the techniques described will have three important advantages over the equivalent synchronous systolic array: faster throughput (rate at which data are clocked through a system), reduced design complexity, and greater reliability. The benefits and drawbacks of using the asynchronous technique are highlighted using three wavefront arrays: two one-dimensional multipliers, and a two-dimensional sorter. All three can be built using just one basic building block
Keywords
asynchronous sequential logic; many-valued logics; sequential circuits; asynchronous wavefront array; design complexity; four state asynchronous architectures; one-dimensional multipliers; reliability; throughput; two-dimensional sorter; CMOS logic circuits; Clocks; Costs; Delay; Logic arrays; Logic design; Protocols; Systolic arrays; Throughput; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.123391
Filename
123391
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