Title :
The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p/sup -/ Si substrate
Author :
Han-Su Kim ; Kyuchul Chong ; Ya-Hong Xie ; Jenkins, K.A.
Author_Institution :
Dept. of Mater. Sci. & Eng., Univ. of California, Los Angeles, CA, USA
Abstract :
Locally incorporated porous Si (PS) trenches are used for radio frequency (RF) crosstalk isolation through p/sup -/ Si substrates. PS trenches provide large dielectric separation (large impedance) between the noise producing and the noise sensitive circuits without prohibitively high stress from a thermal expansion coefficient mismatch between bulk Si and the common dielectrics, e.g. SiO2 and Si3N4. A variety of commonly used RF isolation structures are fabricated and compared. The best isolation structure for the p/sup $/substrates is shown to be the one with p/sup +/ grounding stripes in addition to a PS trench. Crosstalk between Al pads with 800 μm separation is reduced to the level comparable to that through air. It is shown that contrary to our previous result using PS trenches in p/sup +/ substrates, p/sup +/ grounding stripes or PS trenches alone is quite ineffective. Superior RF isolation is achieved only when the two approaches are used in conjunction with one another. The combined approach results in additional crosstalk reduction of 21 dB at 2 GHz and 11 dB at 20 GHz.
Keywords :
CMOS integrated circuits; crosstalk; elemental semiconductors; integrated circuit noise; isolation technology; mixed analogue-digital integrated circuits; porous semiconductors; radiofrequency integrated circuits; silicon; silicon-on-insulator; substrates; 2 to 20 GHz; 800 micron; Al; Al pads; RF crosstalk reduction; RF isolation structures; RFICs; Si; SiO/sub 2/; distributed grounding; mixed-signal ICs; p/sup +/ grounding stripes; p/sup -/ Si substrate; porous Si trenches; radiofrequency crosstalk isolation; Circuit noise; Crosstalk; Dielectric substrates; Grounding; Impedance; Isolation technology; Radio frequency; Semiconductor device noise; Testing; Thermal stresses;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.818071