Abstract :
An inexpensive, compact, low-power glass delay line memory PHA, functionally designed for educational, as distinct from research applications, is described. Using series 74 I/C logic and consuming 20W with CRT display, it performs the basic sorting function, can be strobed, and contains a three-stage digital buffer derandomizer giving it virtually zero resolving time up to 8 kp/s input. The novel logic schemes are described.
