A 34-ns 16-Mb DRAM with controllable voltage down-converter

Author

Hidaka, Hideto ; Arimoto, Kazutami ; Hirayama, Kazutoshi ; Hayashikoshi, Masanori ; Asakura, Mikio ; Tsukude, Masaki ; Oishi, Tsukasa ; Kawai, Shinji ; Suma, Katsuhiro ; Konishi, Yasuhiro ; Tanaka, Koji ; Wakamiya, Wataru ; Ohno, Yoshikazu ; Fujishima, Ka

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

27

Issue

7

fYear

1992

fDate

7/1/1992 12:00:00 AM

Firstpage

1020

Lastpage

1027

Abstract

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity.

Keywords

DRAM chips; circuit reliability; decoding; integrated circuit testing; ion implantation; life testing; 16 Mbit; 34 ns; DRAM; accelerated life-test function; access time; controllable voltage down-converter; fully embedded sense-amplifier driving scheme; latch-up immunity; megaelectronvolt ion-implantation process; multidivided column address decoding scheme; process sequence; reliability; retrograded well structure; soft error; substrate engineering technology; Acceleration; Circuits; Decoding; Power dissipation; Power engineering and energy; Power generation; Power supplies; Random access memory; Reliability engineering; Ultra large scale integration; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.142597

Filename

142597