Title :
On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM
Author :
Schuster, Stanley E. ; Chappell, Terry I. ; Chappell, Barbara A. ; Franch, Robert L.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
7/1/1992 12:00:00 AM
Abstract :
On-chip test circuitry that provides 8-b-deep emitter-coupled logic (ECL) level patterns to 12 input pads of a 512-kb CMOS ECL static RAM (SRAM) at cycle times as fast as 1.4 ns has been built in a 0.8- mu m CMOS technology with Leff=0.5 mu m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide an optimum setup time and data-valid windows as the operating frequency changes is described. Measured results and extensive simulation demonstrate the stability of the on-chip test circuitry for cycle times of 1.4-50 ns. The on-chip test circuitry makes it possible to test the SRAM chip at its pipelined cycle time. In addition, the speed of the on-chip test circuitry will track future technology improvements, making it possible to generate test patterns as SRAM performance continues to improve.
Keywords :
CMOS integrated circuits; SRAM chips; built-in self test; emitter-coupled logic; integrated circuit testing; 0.8 micron; 1.4 to 50 ns; 512 kbit; CMOS ECL SRAM; chip-select signal; cycle times; data-valid windows; emitter-coupled logic; on-chip test circuitry; operating frequency; optimum setup time; pipelined cycle time; static RAM; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit stability; Circuit testing; Frequency synchronization; Logic testing; Random access memory; SRAM chips; Semiconductor device measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
