Title :
Ciphering hardware for high-speed digital networks: a REDOC III implementation
Author_Institution :
Dept. of Electr. & Electron. Eng., Bradford Univ., UK
fDate :
5/25/1995 12:00:00 AM
Abstract :
REDOC III, an algorithm for data ciphering with a predicted throughput in hardware of over 1 Gbit/s, is a proposed replacement for DES. A Xilinx 4000 implementation, with simulation results that confirm the potential system performances, is reported
Keywords :
cryptography; digital communication; field programmable gate arrays; logic partitioning; 1 Gbit/s; REDOC III implementation; Xilinx 4000 implementation; data ciphering; data security; encryption algorithm; high-speed digital networks; predicted throughput;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950576
