Synthesis tools help teach systems concepts in VLSI design

The VLSI project class at Princeton University has been redesigned, using modern logic and layout synthesis tools, to emphasize system design issues. The design methodology taught in the class allows students to build larger designs; it also allows them to learn, by redesign, how to trade off layout, circuit, logic, and architectural design problems. Two synthesis tools were developed (based on the Oct tool set from UC Berkeley) to generate standard cell layouts: one which takes as input finite-state machine transition tables; and one which generates netlists using C programs. The author describes; what is important for students to learn in a VLSI design class; the design methodology developed to teach this curriculum through a design project; and the CAD tools used to support this design methodology