Low-power single-bit full adder cells

The single-bit full adder is one of the main components in almost all logic structures. The performance of logic structures is highly dependent on the adder cells. This paper discusses the performance of single-bit full adders and presents a performance analysis for those cells in CMOS technology. Fourteen single-bit full adders and three new adders, a total of different adder cells, are analyzed in terms of power and delay using 0.35, 0.25 and 0.18 µm TSMC CMOS technology. In addition, this paper discusses the charging-capability parameter of the adder cells, which represents the fan-out of each cell. The charging-capability parameter is capable of describing the performance of the adder cell in a large, as yet unbuilt structure. Hence, the performance analysis of the single-bit full adder relates the design to power, delay, and charging capability of the logic components.