A configurable convolution chip with programmable coefficients

Describes the architecture and implementation of a bit-level configurable convolver array. The systolic field supports a configuration during operation in terms of number of taps and coefficient word length. A chip has been designed in 1.5- mu m CMOS using a full-custom design style which contains 112586 transistors on an active area of 46 mm². The configurability consumes only 9% of that area. The prototypes are shown to be fully functional up to 20 MHz. An extension of the architecture for optimized calculation of transformations is also presented.