DocumentCode
795515
Title
Random access at double the speed
Author
Geppert, N.
Volume
39
Issue
8
fYear
2002
fDate
8/1/2002 12:00:00 AM
Firstpage
20
Lastpage
21
Abstract
Unveiled at the IEEE´s Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.
Keywords
DRAM chips; application specific integrated circuits; embedded systems; 512 Kbit; ASIC; IBM demonstration chip; architectural device; circuit blocks; dynamic memory architecture; embedded DRAM; macros; on-chip memory applications; systems-on-chip; write-back buffer; Application specific integrated circuits; Embedded computing; Logic arrays; Logic testing; Microprocessors; Random access memory; Read-write memory; Tellurium; Very large scale integration; Writing;
fLanguage
English
Journal_Title
Spectrum, IEEE
Publisher
ieee
ISSN
0018-9235
Type
jour
DOI
10.1109/MSPEC.2002.1021947
Filename
1021947
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