Title :
Random access at double the speed
fDate :
8/1/2002 12:00:00 AM
Abstract :
Unveiled at the IEEE´s Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.
Keywords :
DRAM chips; application specific integrated circuits; embedded systems; 512 Kbit; ASIC; IBM demonstration chip; architectural device; circuit blocks; dynamic memory architecture; embedded DRAM; macros; on-chip memory applications; systems-on-chip; write-back buffer; Application specific integrated circuits; Embedded computing; Logic arrays; Logic testing; Microprocessors; Random access memory; Read-write memory; Tellurium; Very large scale integration; Writing;
Journal_Title :
Spectrum, IEEE
DOI :
10.1109/MSPEC.2002.1021947
