Title :
Chip-in-the-loop learning algorithm for Boltzmann machine
Author :
Klein, J.O. ; Pujol, H. ; Garda, P.
Author_Institution :
Inst. d´´Electron. Fondamentale, Univ. de Paris-Sud, Orsay, France
fDate :
6/8/1995 12:00:00 AM
Abstract :
A new algorithm is presented for chip-in-the-loop learning of the synchronous Boltzmann machine, which has two distinct advantages: it allows optimal use of analogue circuit dynamic range, unlike the conventional learning algorithm, and it features a coherent dual weight representation, which improves learning efficiency
Keywords :
Boltzmann machines; analogue computer circuits; learning (artificial intelligence); neural chips; analogue circuit; chip-in-the-loop learning algorithm; coherent dual weight representation; dynamic range; learning efficiency; synchronous Boltzmann machine;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950685
